The present invention generally relates to a packet switching system having a bus matrix switch, and more particularly to a packet switching system which includes a bus matrix switch having a plurality of buses arranged into a matrix and transfer buffers provided at cross points of the buses.
Recently, a packet switching network for transferring a variety of data has become practical to use. In some packet switching networks, switching of packet data is realized by a matrix switch having buses arranged into a matrix and transfer buffers provided at cross points of the buses. A packet incoming through an input path (bus) is temporarily stored in a transfer buffer and then sent to an output path (bus) connected to a destination terminal. The basic concept of packet switching networks is directed to realizing packet switching by means of parallel processing implemented by hardware as well as simplifying protocols of packet switching so that throughput at switch nodes is improved.
Referring to FIG. 1, there is illustrated a conventional packet switching system which employs a bus matrix switch. The packet switching system shown in FIG. 1 includes packet transfer controllers 100, input packet transfer buses 103, output packet transfer buses 104 and transfer buffers 105 (#00-#nn). One packet controller 100 and one input packet transfer bus 103 are provided for each of the transfer buffers #00-#nn. It will be noted that the first digit of the number assigned to each transfer buffer 105 indicates a corresponding input packet transfer bus, and the second digit thereof indicates one of the transfer buffers connected to the input packet transfer bus indicated by the first digit. Each of the packet transfer controllers 100 is made up of a receive packet transfer controller 101 and a send packet transfer controller 102. The receive packet transfer controller 101 operates independently of the send packet transfer controller 102.
A bus matrix switch is composed of the input packet transfer buses 103, the output packet transfer buses 104 and the transfer buffers 105. A switching operation is as follows. It is now assumed that the receive packet transfer controller 101 of the packet transfer controller 100 labeled #0 receives a packet and sends the same to the input packet transfer bus 103 labeled #0. The packet on the input packet transfer bus 103 is input to the transfer buffer 105 which is connected to the output packet transfer bus 104 to which a destination terminal is connected. The packet is temporarily stored in the transfer buffer being considered and is then sent to the send packet transfer controller 102 through the corresponding output packet transfer bus 104.
The packet sent to the input packet transfer bus 103 includes information (packet header) representative of a destination terminal to which the present packet is to be sent. When the above-mentioned information is detected by the transfer buffer 105 connected to the output packet transfer bus 104 to which the destination terminal is connected, it becomes possible for the transfer buffer 105 being considered to enter the packet. Then the packet is read out from the transfer buffer 105 and then sent to the corresponding send packet transfer controller 102. Then the packet is sent to the destination terminal from the send packet transfer controller 102.
The above-mentioned prior packet switching system in FIG. 1 has disadvantages as described below. The packet switching system handles a variety of data. When the packet switching system processes a large amount of multi-media data, the following problems take place. In many cases, multi-media data is generated in the form of burst. Thus, it is difficult to estimate the distribution of generated multi-media data on the time base. From this point of view, there is a possibility that the traffic concentrates at a specific transfer buffer in the bus matrix switch. When the traffic concentrates at a specific transfer buffer, it overflows with packets and thus some packets are destroyed or lost (hereafter this is referred to as blocking). In order to overcome this problem, it is necessary to use transfer buffers having a large capacity and control the traffic so as to be sufficiently small on the input side of the bus matrix switch. However, the use of large-capacity transfer buffers needs an increased scale of hardware. In addition, the storage capacity of each transfer buffer is proportional to the number of input packet transfer buses 103. When the system is expanded so that new input packet transfer buses are added, the storage capacity of each transfer buffer must be increased depending on the number of the added input packet transfer buses. Thus, it is desired that the system be expanded without increasing the storage capacity of each transfer buffer.